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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Root complex</span></span>
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<p>In a <a href="PCI_Express" title="PCI Express">PCI Express</a> (PCIe) system, a <b>root complex</b> device connects the CPU and memory subsystem to the PCI Express switch fabric composed of one or more PCIe or PCI devices. A root complex is sometimes referred to <b>PCI root bridge</b>.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>
</p><p>The root complex generates transaction requests on behalf of the <a href="CPU" class="mw-redirect" title="CPU">CPU</a>, which is interconnected through a local bus. Root complex functionality may be integrated in the chipset and/or the CPU. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
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<div class="mw-heading mw-heading2"><h2 id="Device_Memory_Map">Device Memory Map</h2></div>
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<p>The PCIe Root Complex holds a master copy of a 'Type 1 Configuration Table' that defines the host memory space that is accessible from each Endpoint device. In addition, each PCIe Endpoint device holds a master copy of their own memory space map in the host system memory as a 'Type 0 Configuration Table', this configuration table in each device allows the host to access the local memory of a PCIe device. Both the Type 1 and Type 0 configuration tables are set up by the Host Operating System that controls the Root Complex by a process known as enumeration and which acts to build a device memory map for the system by querying each bridge, and endpoint device connected on the bus network. Similarly, a PCIe Bridge acts a tiered root complex with a "Type 0 Configuration Table".
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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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</style><cite id="CITEREFRichard_Solomon2015" class="citation web cs1">Richard Solomon (2015-06-17). <a rel="nofollow" class="external text" href="https://pcisig.com/sites/default/files/files/PCI_Express_Basics_Background.pdf#page=26">"PCI Express Basics and Background"</a> <span class="cs1-format">(PDF)</span>. <a href="PCI-SIG" title="PCI-SIG">PCI-SIG</a>. p. 26<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-04-12</span></span>.</cite></span>
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<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://uefi.org/specs/UEFI/2.10/14_Protocols_PCI_Bus_Support.html">"14. Protocols — PCI Bus Support — UEFI Specification 2.10 documentation"</a>. <i>uefi.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-11-16</span></span>.</cite></span>
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<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110221044635/http://www.rtcmagazine.com/articles/view/100327">"Choosing the Right Programmable Logic Solution for PCI Express Applications"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.rtcmagazine.com/articles/view/100327">the original</a> on 21 February 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">31 March</span> 2010</span>.</cite></span>
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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://docs.oracle.com/cd/E19683-01/806-5222/hwovr-22/">"Bus Specifics (Writing Device Drivers)"</a>. <i>docs.oracle.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2020-11-14</span></span>.</cite></span>
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